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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. advance information for pre-production products; subject to change without notice. DSLVDS1002 snls619 ? july 2018 DSLVDS1002 3.3-v lvds single channel high speed differential receiver 1 1 features 1 ? designed for signaling rates up to 400-mbps ? single 3.3v power supply design (3.0-v to 3.6-v range) ? 100-ps typical differential skew ? 3.5-ns maximum propagation delay ? accepts small swing ( 350-mv typical) differential signal levels ? power off protection (high impedance on lvds inputs) ? flow-through pinout simplifies pcb layout ? low power dissipation (10 mw typical@ 3.3 v static) ? lvds receiver inputs accept lvds/blvds/lvpecl inputs ? failsafe protection for open, short and terminated inputs ? sot-23 5-lead package ? meets or exceeds ansi tia/eia-644-a standard ? industrial temperature operating range ( ? 40 c to +85 c) 2 applications ? board to board communication ? test and measurement ? motor drive ? wireless infrastructure ? telecom infrastructure ? printer ? multi function printer ? professional video cameras ? enterprise and cinema projectors ? led video wall ? nic card ? rack server ? ultrasound scanners 3 description the DSLVDS1002 is a single channel low voltage differential signaling (lvds) receiver designed for applications requiring low power dissipation, low noise and high data rates. in addition, the short circuit fault current is also minimized. the DSLVDS1002 device is designed to support data rates that are at least 400 mbps (200 mhz) utilizing lvds technology. the DSLVDS1002 accepts low voltage ( 350-mv typical) differential input signals and outputs a 3.3-v cmos/ttl signal. the receivers also support open, shorted, and terminated (100 ? ) input fail-safe. the receiver output will be high for all fail-safe conditions. the DSLVDS1002 is in a 5-lead sot-23 package that is designed for easy pcb layout. the DSLVDS1002 can be paired with its companion single line driver, dslvds1001, or with any lvds driver, to provide a high-speed lvds interference. device information (1) part number package body size (nom) DSLVDS1002 sot-23 dbv 3.00 mm x 3.00 mm (1) for all available packages, see the orderable addendum at the end of the datasheet. functional block diagram typical application lvcmos/ lvttl out in + in - ep blue vcc gnd DSLVDS1002 receiver driver 100 lvcmos/lvttl out in + in - dslvds1001 advance information technical documents support &community ordernow productfolder tools & software
2 DSLVDS1002 snls619 ? july 2018 www.ti.com product folder links: DSLVDS1002 submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 truth table ............................................................. 3 7 specifications ......................................................... 4 7.1 absolute maximum ratings ...................................... 4 7.2 esd ratings .............................................................. 4 7.3 recommended operating conditions ....................... 4 7.4 thermal information (3-pkg option) [delete me if not used] .......................................................................... 4 7.5 electrical characteristics ........................................... 5 7.6 switching characteristics .......................................... 6 8 parameter measurement information .................. 7 9 detailed description .............................................. 8 9.1 overview ................................................................... 8 9.2 functional block diagram ......................................... 8 9.3 feature description ................................................... 8 9.4 device functional modes .......................................... 8 10 application and implementation ........................ 11 10.1 application information .......................................... 11 10.2 typical application ............................................... 11 11 power supply recommendations ..................... 14 11.1 power supply considerations ............................... 14 12 layout ................................................................... 15 12.1 layout guidelines ................................................. 15 12.2 layout example .................................................... 18 13 device and documentation support ................. 19 13.1 receiving notification of documentation updates 19 13.2 community resources .......................................... 19 13.3 trademarks ........................................................... 19 13.4 electrostatic discharge caution ............................ 19 13.5 glossary ................................................................ 19 14 mechanical, packaging, and orderable information ........................................................... 20 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. date revision notes july 2018 * initial release. advance information
3 DSLVDS1002 www.ti.com snls619 ? july 2018 product folder links: DSLVDS1002 submit documentation feedback copyright ? 2018, texas instruments incorporated 5 pin configuration and functions dvb package 5-pin sot-23 top view pin functions package pin number pin name description sot-23 1 v dd power supply pin, +3.3v 0.3v 2 gnd ground pin 3 in + non-inverting receiver input pin 4 in - inverting receiver input pin 5 lvcmos/lvttl out lvttl/lvcmos receiver output pin 6 truth table inputs output v id = [in+] ? [in ? ] ttl out v id 0v h v id ? 0.1v l full fail-safe open/short or terminated h advance information
4 DSLVDS1002 snls619 ? july 2018 www.ti.com product folder links: DSLVDS1002 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7 specifications 7.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit supply voltage (v dd ) -0.3 4 v input voltage (in+, in ? ) -0.3 3.9 v output voltage (ttl out) -0.3 vdd + 0.3 v output short circuit current -100 ma package power dissipation 25 c dbv package 902 mw derate dbv package 7.22 25 mw/ c lead temperature soldering (4 sec.) 260 c junction temperature 150 c storage temperature, t stg -65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. pins listed as 2000 v may actually have higher performance. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. pins listed as 2000 v may actually have higher performance. 7.2 esd ratings value unit v (esd) electrostatic discharge human body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v charged-device model (cdm), per jedec specification jesd22- c101 (2) 2000 7.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit supply voltage (v dd ) +2.7 +3.3 +3.6 v operating free air temperature (t a ) ? 40 25 +85 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report, spra953 . 7.4 thermal information (3-pkg option) [delete me if not used] thermal metric (1) DSLVDS1002 unit sot-23 (dvb) 5 pins r ja junction-to-ambient thermal resistance 189.9 c/w r jc(top) junction-to-case (top) thermal resistance 101.2 c/w r jb junction-to-board thermal resistance 49.7 c/w jt junction-to-top characterization parameter 17.5 c/w jb junction-to-board characterization parameter 49 c/w r jc(bot) junction-to-case (bottom) thermal resistance n/a c/w advance information
5 DSLVDS1002 www.ti.com snls619 ? july 2018 product folder links: DSLVDS1002 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) current into device pins is defined as positive. current out of device pins is defined as negative. all voltages are referenced to ground unless otherwise specified (such as v id ). (2) output short circuit current (i os ) is specified as magnitude only, minus sign indicates direction only. only one output should be shorted at a time, do not exceed maximum junction temperature specification. 7.5 electrical characteristics over supply voltage and operating temperature ranges, unless otherwise specified. (1) parameter test conditions pin min typ max unit v th differential input high threshold valid across the specified common mode voltage (v cm ) range. in+, in ? 100 mv v tl differential input low threshold ? 100 ? 30 mv v cm common-mode voltage v dd = 2.7v, v id = 100mv 0.05 2.35 v v dd = 3.0v to 3.6v, v id = 100mv 0.05 v dd - 0.3v v i in input current v in = +2.8v v dd = 3.6v or 0v ? 15 1 15 a v in = 0v ? 15 1 15 a v in = +3.6v v dd = 0v ? 20 +20 a i in change in magnitude of i in v in = +2.8v v dd = 3.6v or 0v 4 a v in = 0v 4 a v in = +3.6v v dd = 0v 4 a i ind differential input current v in+ = +0.4v, v in ? = +0v 3 3.9 4.4 ma c in input capacitance in+ = in ? = gnd 3 pf v oh output high voltage i oh = ? 0.4 ma, v id = +200 mv ttl out 2.4 3.1 v i oh = ? 0.4 ma, inputs terminated 2.4 3.1 v i oh = ? 0.4 ma, inputs shorted 2.4 3.1 v v ol output low voltage i ol = 2 ma, v id = ? 200 mv 0.3 0.5 v i os output short circuit current v out = 0v (2) ? 15 ? 50 ? 100 ma v cl input clamp voltage i cl = ? 18 ma ? 1.5 ? 0.7 v i dd no load supply current inputs open v dd 5.4 9 ma advance information
6 DSLVDS1002 snls619 ? july 2018 www.ti.com product folder links: DSLVDS1002 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) t skd1 is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of the same channel. (2) t skd3 , part to part skew, is the differential channel-to-channel skew of any event between devices. this specification applies to devices at the same v dd and within 5 c of each other within the operating temperature range. (3) t skd4 , part to part skew, is the differential channel-to-channel skew of any event between devices. this specification applies to devices over the recommended operating temperature and voltage ranges, and across process distribution. t skd4 is defined as |max ? min| differential propagation delay. (4) f max generator input conditions: t r = t f < 1 ns (0% to 100%), 50% duty cycle, differential (1.05v to 1.35 peak to peak). output criteria: 60%/40% duty cycle, v ol (max 0.4v), v oh (min 2.4v), load = 15 pf (stray plus probes). the parameter is ensured by design. the limit is based on the statistical analysis of the device over the pvt range by the transition times (t tlh and t thl ). 7.6 switching characteristics over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit t phld differential propagation delay high to low c l = 15 pf 1.0 1.8 3.5 ns t plhd differential propagation delay low to high v id = 200 mv 1.0 1.7 3.5 ns t skd1 differential pulse skew |t phld ? t plhd | (1) ( figure 1 and figure 2 ) 0 100 400 ps t skd3 differential part to part skew (2) 0 0.3 1.0 ns t skd4 differential part to part skew (3) 0 0.4 1.5 ns t tlh rise time 500 ps t thl fall time 500 ps f max maximum operating frequency (4) 200 250 mhz advance information
7 DSLVDS1002 www.ti.com snls619 ? july 2018 product folder links: DSLVDS1002 submit documentation feedback copyright ? 2018, texas instruments incorporated 8 parameter measurement information figure 1. receiver propagation delay and transition time test circuit figure 2. receiver propagation delay and transition time waveforms advance information
8 DSLVDS1002 snls619 ? july 2018 www.ti.com product folder links: DSLVDS1002 submit documentation feedback copyright ? 2018, texas instruments incorporated 9 detailed description 9.1 overview the DSLVDS1002 is a single channel, low voltage differential signaling (lvds) line receiver. it operates from a single power supply that is nominally 3.3-v, but can be as low as 3.0-v and as high as 3.6-v. the input to the DSLVDS1002 is a differential signal complying with the lvds standard (tia/eia-644) and the output is a 3.3-v lvcmos/lvttl signal. the differential input signal operates with a signal level of 340 mv, nominally, at common-mode voltage of 1.2-v. the differential nature of the inputs provides immunity to common-mode coupled signals that the driven signal may experience. a termination resistor of 100- should be selected to match the media, and should be located as close to the receiver as possible. 9.2 functional block diagram 9.3 feature description the DSLVDS1002 is capable of detecting signals as low as 100-mv, over a 1-v common-mode range centered around 1.2-v. the ac parameters of the input pins are optimized for a recommended operating input voltage range of 0-v to 2.4-v (measured from each pin to ground). the device will operate for receiver input voltages up to v dd , but exceeding v dd will turn on the esd protection circuitry which will clamp the bus voltages. 9.4 device functional modes 9.4.1 termination use a termination resistor which best matches the differential impedance or your transmission line. the resistor should be between 90 ? and 130 ? . remember that the current mode outputs need the termination resistor to generate the differential voltage. lvds will not work without resistor termination. typically, connecting a single resistor across the pair at the receiver end will suffice. surface mount 1% - 2% resistors are the best. pcb stubs, component lead, and the distance from the termination to the receiver inputs should be minimized. the distance between the termination resistor and the receiver should be < 10mm (12mm max). 9.4.2 threshold the lvds standard (ansi/tia/eia-644-a) specifies a maximum threshold of 100mv for the lvds receiver. the DSLVDS1002 supports an enhanced threshold region of ? 100mv to 0v. this is useful for fail-safe biasing. the threshold region is shown in the voltage transfer curve (vtc) in figure 4. the typical DSLVDS1002 lvds receiver switches at about ? 30mv. note that with v id = 0v, the output will be in a high state. with an external fail-safe bias of +25mv applied, the typical differential noise margin is now the difference from the switch point to the bias point. in the example below, this would be 55mv of differential noise margin (dnm) (+25mv ? ( ? 30mv)). with the enhanced threshold region of ? 100mv to 0v, this small external fail-safe biasing of +25mv (with respect to 0v) gives a dnm of a comfortable 55mv. with the standard threshold region of 100mv, the external fail-safe biasing would need to be +25mv with respect to +100mv or +125mv, giving a dnm of 155mv which is stronger fail-safe biasing than is necessary for the DSLVDS1002. if more dnm is required, then a stronger fail-safe bias point can be set by changing resistor values. figure 3. vtc of the DSLVDS1002 lvds receiver lvcmos/ lvttl out in + in - advance information
9 DSLVDS1002 www.ti.com snls619 ? july 2018 product folder links: DSLVDS1002 submit documentation feedback copyright ? 2018, texas instruments incorporated device functional modes (continued) 9.4.3 fail-safe feature the lvds receiver is a high gain, high speed device that amplifies a small differential signal (20mv) to lvcmos/lvttl logic levels. due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal. the receiver's internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe protection (a stable known state of high output voltage) for floating, terminated or shorted receiver inputs. 1. open input pins. it is not required to tie the receiver inputs to ground or any supply voltage. internal failsafe circuitry will ensure a high, stable output state for open inputs. 2. terminated input. if the driver is disconnected (cable unplugged), or if the driver is in a power-off condition, the receiver output will again be in a high state, even with the end of cable 100 termination resistor across the input pins. the unplugged cable can become a floating antenna which can pick up noise. if the cable picks up more than 10mv of differential noise, the receiver may see the noise as a valid signal and switch. to insure that any noise is seen as common-mode and not differential, a balanced interconnect should be used. twisted pair cable will offer better balance than flat ribbon cable. 3. shorted inputs. if a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0v differential input voltage, the receiver output will remain in a high state. shorted input fail-safe is not supported across the common-mode range of the device (gnd to 2.4v). it is only supported with inputs shorted and no external common-mode voltage applied. external lower value pull up and pull down resistors (for a stronger bias) may be used to boost fail-safe in the presence of higher noise levels. the pull up and pull down resistors should be in the 5k ? to 15k ? range to minimize loading and waveform distortion to the driver. the common-mode bias point should be set to approximately 1.2v (less than 1.75v) to be compatible with the internal circuitry. the DSLVDS1002 is compliant to the original ansi eia/tia-644 specification and is also compliant to the new ansi eia/tia-644-a specification with the exception the newly added i in specification. due to the internal fail- safe circuitry, i in cannot meet the 6 a maximum specified. this exception will not be relevant unless more than 10 receivers are used. additional information on fail-safe biasing of lvds devices may be found in an-1194 failsafe biasing of lvds interfaces ( snla051 ). 9.4.4 probing lvds transmission lines always use high impedance ( > 100k ? ), low capacitance ( < 2 pf) scope probes with a wide bandwidth (1 ghz) scope. improper probing will give deceiving results. advance information
10 DSLVDS1002 snls619 ? july 2018 www.ti.com product folder links: DSLVDS1002 submit documentation feedback copyright ? 2018, texas instruments incorporated device functional modes (continued) 9.4.5 cables and connectors, general comments when choosing cable and connectors for lvds it is important to remember: use controlled impedance media. the cables and connectors you use should have a matched differential impedance of about 100 ? . they should not introduce major impedance discontinuities. balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax) for noise reduction and signal quality. balanced cables tend to generate less emi due to field canceling effects and also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by the receiver. for cable distances < 0.5m, most cables can be made to work effectively. for distances 0.5m d 10m, cat 3 (category 3) twisted pair cable works well, is readily available and relatively inexpensive. advance information
11 DSLVDS1002 www.ti.com snls619 ? july 2018 product folder links: DSLVDS1002 submit documentation feedback copyright ? 2018, texas instruments incorporated 10 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 10.1 application information the DSLVDS1002 device is a single-channel lvds receiver. the functionality of this device is simple, yet extremely flexible, leading to its use in designs ranging from wireless base stations to desktop computers. the varied class of potential applications share features and applications discussed in the paragraphs below. 10.2 typical application 10.2.1 point-to-point communications the most basic application for lvds buffers, as found in this data sheet, is for point-to-point communications of digital data, as shown in figure 4 . figure 4. typical application a point-to-point communications channel has a single transmitter (driver) and a single receiver. this communications topology is often referred to as simplex. in figure 4 the driver receives a single-ended input signal and the receiver outputs a single-ended recovered signal. the lvds driver converts the single-ended input to a differential signal for transmission over a balanced interconnecting media of 100- characteristic impedance. the conversion from a single-ended signal to an lvds signal retains the digital data payload while translating to a signal whose features are more appropriate for communication over extended distances or in a noisy environment. 10.2.2 design requirements design parameters example value receiver supply voltage (v cc ) 3.0 to 3.6 v receiver output voltage 0 to 3.6 v signaling rate 0 to 400 mbps interconnect characteristic impedance 100 termination resistance 100 number of receiver nodes 1 ground shift between driver and receiver 1 v ep blue vcc gnd DSLVDS1002 receiver driver 100 lvcmos/lvttl out in + in - dslvds1001 advance information
12 DSLVDS1002 snls619 ? july 2018 www.ti.com product folder links: DSLVDS1002 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) howard johnson & martin graham.1993. high speed digital design ? a handbook of black magic. prentice hall prt. isbn number 013395724. 10.2.3 detailed design procedure 10.2.3.1 receiver bypass capacitance bypass capacitors play a key role in power distribution circuitry. specifically, they create low-impedance paths between power and ground. at low frequencies, a good digital power supply offers very low-impedance paths between its terminals. however, as higher frequency currents propagate through power traces, the source is quite often incapable of maintaining a low-impedance path to ground. bypass capacitors are used to address this shortcoming. usually, large bypass capacitors (10 f to 1000 f) at the board-level do a good job up into the khz range. due to their size and length of their leads, they tend to have large inductance values at the switching frequencies of modern digital circuitry. to solve this problem, one must resort to the use of smaller capacitors (nf to f range) installed locally next to the integrated circuit. multilayer ceramic chip or surface-mount capacitors (size 0603 or 0805) minimize lead inductances of bypass capacitors in high-speed environments, because their lead inductance is about 1 nh. for comparison purposes, a typical capacitor with leads has a lead inductance around 5 nh. the value of the bypass capacitors used locally with lvds chips can be determined by the following formula according to johnson (1) , equations 8.18 to 8.21. a conservative rise time of 200 ps and a worst-case change in supply current of 1 a covers the whole range of lvds devices offered by texas instruments. in this example, the maximum power supply noise tolerated is 200 mv; however, this figure varies depending on the noise budget available in your design. (1) (1) (2) the following example lowers lead inductance and covers intermediate frequencies between the board-level capacitor ( > 10 f) and the value of capacitance found above (0.001 f). you should place the smallest value of capacitance as close as possible to the chip. figure 5. recommended lvds bypass capacitor layout 10.2.3.2 interconnecting media the physical communication channel between the driver and the receiver may be any balanced paired metal conductors meeting the requirements of the lvds standard, the key points which will be included here. this media may be a twisted pair, twinax, flat ribbon cable, or pcb traces. the nominal characteristic impedance of the interconnect should be between 100 and 120 with variation no more than 10% (90 to 132 ). 10.2.3.3 pcb transmission lines as per snla187 , figure 6 depicts several transmission line structures commonly used in printed-circuit boards (pcbs). each structure consists of a signal line and a return path with uniform cross-section along its length. a microstrip is a signal trace on the top (or bottom) layer, separated by a dielectric layer from its return path in a ground or power plane. a stripline is a signal trace in the inner layer, with a dielectric layer in between a ground plane above and below the signal trace. the dimensions of the structure along with the dielectric material properties determine the characteristic impedance of the transmission line (also called controlled-impedance transmission line). lvds 1a c 200 ps 0.001 f 0.2v ? ? = = m ? ? maximum step change supply current chip rise time maximum power supply noise i c t v d ? ? = ? d ? advance information 0.1 f 0.001 f 3.3 v
13 DSLVDS1002 www.ti.com snls619 ? july 2018 product folder links: DSLVDS1002 submit documentation feedback copyright ? 2018, texas instruments incorporated when two signal lines are placed close by, they form a pair of coupled transmission lines. figure 6 shows examples of edge-coupled microstrip lines, and edge-coupled or broad-side-coupled striplines. when excited by differential signals, the coupled transmission line is referred to as a differential pair. the characteristic impedance of each line is called odd-mode impedance. the sum of the odd-mode impedances of each line is the differential impedance of the differential pair. in addition to the trace dimensions and dielectric material properties, the spacing between the two traces determines the mutual coupling and impacts the differential impedance. when the two lines are immediately adjacent; for example, s is less than 2w, the differential pair is called a tightly- coupled differential pair. to maintain constant differential impedance along the length, it is important to keep the trace width and spacing uniform along the length, as well as maintain good symmetry between the two lines. figure 6. controlled-impedance transmission lines 0 r 87 5.98 h z ln 0.8 w t 1.41 ? h ? 1 > @ > @ 0 r 1.9 2 h t 60 z ln 0.8 w t ? ? h ? 1 s 0.96 h diff 0 z 2 z 1 0.48 e u ? u u u ? ? 1 s 2.9 h diff 0 z 2 z 1 0.347e u ? u u ? ? 1 co-planar coupled microstrips broad-side coupled striplines edge-coupled edge-coupled single-ended microstrip single-ended stripline w h t w t h h s h differential microstrip differential stripline s h s h h g g w w w s advance information
14 DSLVDS1002 snls619 ? july 2018 www.ti.com product folder links: DSLVDS1002 submit documentation feedback copyright ? 2018, texas instruments incorporated 11 power supply recommendations 11.1 power supply considerations the dslvds1001 driver is designed to operate from a single power supply with supply voltage in the range of 3.0 v to 3.6 v. in a typical application, a driver and a receiver may be on separate boards, or even separate equipment. in these cases, separate supplies would be used at each location. the expected ground potential difference between the driver power supply and the receiver power supply would be less than | 1 v|. board level and local device level bypass capacitance should be used. advance information
15 DSLVDS1002 www.ti.com snls619 ? july 2018 product folder links: DSLVDS1002 submit documentation feedback copyright ? 2018, texas instruments incorporated (2) howard johnson & martin graham.1993. high speed digital design ? a handbook of black magic. prentice hall prt. isbn number 013395724. (3) mark i. montrose. 1996. printed circuit board design techniques for emc compliance. ieee press. isbn number 0780311310. (4) clyde f. coombs, jr. ed, printed circuits handbook, mcgraw hill, isbn number 0070127549. 12 layout 12.1 layout guidelines 12.1.1 layout guidelines 12.1.1.1 microstrip vs. stripline topologies as per slld009 , printed-circuit boards usually offer designers two transmission line options: microstrip and stripline. microstrips are traces on the outer layer of a pcb, as shown in figure 7 . figure 7. microstrip topology on the other hand, striplines are traces between two ground planes. striplines are less prone to emissions and susceptibility problems because the reference planes effectively shield the embedded traces. however, from the standpoint of high-speed transmission, juxtaposing two planes creates additional capacitance. ti recommends routing lvds signals on microstrip transmission lines, if possible. the pcb traces allow designers to specify the necessary tolerances for z o based on the overall noise budget and reflection allowances. footnotes 1 (2) , 2 (3) , and 3 (4) provide formulas for z o and t pd for differential and single-ended traces. (2) (3) (4) figure 8. stripline topology 12.1.1.2 dielectric type and board construction the speeds at which signals travel across the board dictates the choice of dielectric. fr-4, or equivalent, usually provides adequate performance for use with lvds signals. if rise or fall times of lvcmos/lvttl signals are less than 500 ps, empirical results indicate that a material with a dielectric constant near 3.4, such as rogers ? 4350 or nelco n4000-13 is better suited. once the designer chooses the dielectric, there are several parameters pertaining to the board construction that can affect performance. the following set of guidelines were developed experimentally through several designs involving lvds devices: ? copper weight: 15 g or 1/2 oz start, plated to 30 g or 1 oz ? all exposed circuitry should be solder-plated (60/40) to 7.62 m or 0.0003 in (minimum). ? copper plating should be 25.4 m or 0.001 in (minimum) in plated-through-holes. ? solder mask over bare copper with solder hot-air leveling advance information
16 DSLVDS1002 snls619 ? july 2018 www.ti.com product folder links: DSLVDS1002 submit documentation feedback copyright ? 2018, texas instruments incorporated layout guidelines (continued) 12.1.1.3 recommended stack layout following the choice of dielectrics and design specifications, you must decide how many levels to use in the stack. to reduce the lvcmos/lvttl to lvds crosstalk, it is a good practice to have at least two separate signal planes as shown in figure 9 . figure 9. four-layer pcb board note the separation between layers 2 and 3 should be 127 m (0.005 in). by keeping the power and ground planes tightly coupled, the increased capacitance acts as a bypass for transients. one of the most common stack configurations is the six-layer board, as shown in figure 10 . figure 10. six-layer pcb board in this particular configuration, it is possible to isolate each signal layer from the power plane by at least one ground plane. the result is improved signal integrity; however, fabrication is more expensive. using the 6-layer board is preferable, because it offers the layout designer more flexibility in varying the distance between signal layers and referenced planes, in addition to ensuring reference to a ground plane for signal layers 1 and 6. 12.1.1.4 separation between traces the separation between traces depends on several factors; however, the amount of coupling that can be tolerated usually dictates the actual separation. low noise coupling requires close coupling between the differential pair of an lvds link to benefit from the electromagnetic field cancellation. the traces should be 100- ? differential and thus coupled in the manner that best fits this requirement. in addition, differential pairs should have the same electrical length to ensure that they are balanced, thus minimizing problems with skew and signal reflection. in the case of two adjacent single-ended traces, one should use the 3-w rule, which stipulates that the distance between two traces must be greater than two times the width of a single trace, or three times its width measured from trace center to trace center. this increased separation effectively reduces the potential for crosstalk. the same rule should be applied to the separation between adjacent lvds differential pairs, whether the traces are edge-coupled or broad-side-coupled. figure 11. 3-w rule for single-ended and differential traces (top view) layer 4: routed plane (ttl signals) layer 3: power plane layer 2: ground plane layer 1: routed plane (lvds signals) layer 4: ground plane layer 5: ground plane layer 4: routed plane (ttl/cmos signals) layer 3: power plane layer 2: ground plane layer 1: routed plane (lvds signals) t 2 w w ww minimum spacing as defined by pcb vendor lvds pair ttl/cmos trace differential traces single-ended traces s = advance information
17 DSLVDS1002 www.ti.com snls619 ? july 2018 product folder links: DSLVDS1002 submit documentation feedback copyright ? 2018, texas instruments incorporated layout guidelines (continued) you should exercise caution when using autorouters, because they do not always account for all factors affecting crosstalk and signal reflection. for instance, it is best to avoid sharp 90 turns to prevent discontinuities in the signal path. using successive 45 turns tends to minimize reflections. 12.1.1.5 crosstalk and ground bounce minimization to reduce crosstalk, it is important to provide a return path to high-frequency currents that is as close as possible to its originating trace. a ground plane usually achieves this. because the returning currents always choose the path of lowest inductance, they are most likely to return directly under the original trace, thus minimizing crosstalk. lowering the area of the current loop lowers the potential for crosstalk. traces kept as short as possible with an uninterrupted ground plane running beneath them emit the minimum amount of electromagnetic field strength. discontinuities in the ground plane increase the return path inductance and should be avoided. 12.1.1.6 decoupling each power or ground lead of a high-speed device should be connected to the pcb through a low inductance path. for best results, one or more vias are used to connect a power or ground pin to the nearby plane. ideally, via placement is immediately adjacent to the pin to avoid adding trace inductance. placing a power plane closer to the top of the board reduces the effective via length and its associated inductance. figure 12. low inductance, high-capacitance power connection bypass capacitors should be placed close to v dd pins. they can be placed conveniently near the corners or underneath the package to minimize the loop area. this extends the useful frequency range of the added capacitance. small-physical-size capacitors, such as 0402 or even 0201, or x7r surface-mount capacitors should be used to minimize body inductance of capacitors. each bypass capacitor is connected to the power and ground plane through vias tangent to the pads of the capacitor as shown in figure 13 (a). an x7r surface-mount capacitor of size 0402 has about 0.5 nh of body inductance. at frequencies above 30 mhz or so, x7r capacitors behave as low-impedance inductors. to extend the operating frequency range to a few hundred mhz, an array of different capacitor values like 100 pf, 1 nf, 0.03 f, and 0.1 f are commonly used in parallel. the most effective bypass capacitor can be built using sandwiched layers of power and ground at a separation of 2 to 3 mils. with a 2-mil fr4 dielectric, there is approximately 500 pf per square inch of pcb. refer back to figure 5-1 for some examples. many high-speed devices provide a low-inductance gnd connection on the backside of the package. this center dap must be connected to a ground plane through an array of vias. the via array reduces the effective inductance to ground and enhances the thermal performance of the small surface mount technology (smt) package. placing vias around the perimeter of the dap connection ensures proper heat spreading and the lowest possible die temperature. placing high-performance devices on opposing sides of the pcb using two gnd planes (as shown in figure 6 ) creates multiple paths for heat transfer. often thermal pcb issues are the result of one device adding heat to another, resulting in a very high local temperature. multiple paths for heat transfer minimize this possibility. in many cases the gnd dap that is so advance information board thickness approximately 100 mil 2 mil typical 12-layer pcb 4 mil 4 mil 6 mil 6 mil v cc via gnd via top signal layer + gnd fill v dd 1 plane gnd plane signal layer buried capacitor > signal layer gnd plane v dd 2 plane bottom signal layer + gnd fill buried capacitor > gnd plane signal layers v cc plane
18 DSLVDS1002 snls619 ? july 2018 www.ti.com product folder links: DSLVDS1002 submit documentation feedback copyright ? 2018, texas instruments incorporated layout guidelines (continued) important for heat dissipation makes the optimal decoupling layout impossible to achieve due to insufficient pad- to-dap spacing as shown in figure 13 (b). when this occurs, placing the decoupling capacitor on the backside of the board keeps the extra inductance to a minimum. it is important to place the v dd via as close to the device pin as possible while still allowing for sufficient solder mask coverage. if the via is left open, solder may flow from the pad and into the via barrel. this will result in a poor solder connection. figure 13. typical decoupling capacitor layouts 12.2 layout example at least two or three times the width of an individual trace should separate single-ended traces and differential pairs to minimize the potential for crosstalk. single-ended traces that run in parallel for less than the wavelength of the rise or fall times usually have negligible crosstalk. increase the spacing between signal paths for long parallel runs to reduce crosstalk. boards with limited real estate can benefit from the staggered trace layout, as shown in figure 14 . figure 14. staggered trace layout this configuration lays out alternating signal traces on different layers; thus, the horizontal separation between traces can be less than 2 or 3 times the width of individual traces. to ensure continuity in the ground signal path, ti recommends having an adjacent ground via for every signal via, as shown in figure 15 . note that vias create additional capacitance. for example, a typical via has a lumped capacitance effect of 1/2 pf to 1 pf in fr4. figure 15. ground via location (side view) short and low-impedance connection of the device ground pins to the pcb ground plane reduces ground bounce. holes and cutouts in the ground planes can adversely affect current return paths if they create discontinuities that increase returning current loop areas. to minimize emi problems, ti recommends avoiding discontinuities below a trace (for example, holes, slits, and so on) and keeping traces as short as possible. zoning the board wisely by placing all similar functions in the same area, as opposed to mixing them together, helps reduce susceptibility issues. advance information 0402 0402 v dd in in+ (a) (b) layer 6 layer 1 signal trace uninterrupted ground plane signal trace uninterrupted ground plane signal via ground via
19 DSLVDS1002 www.ti.com snls619 ? july 2018 product folder links: DSLVDS1002 submit documentation feedback copyright ? 2018, texas instruments incorporated 13 device and documentation support 13.1 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 13.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 13.3 trademarks e2e is a trademark of texas instruments. rogers is a trademark of rogers corporation. 13.4 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 13.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. advance information
20 DSLVDS1002 snls619 ? july 2018 www.ti.com product folder links: DSLVDS1002 submit documentation feedback copyright ? 2018, texas instruments incorporated 14 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. advance information
package option addendum www.ti.com 3-aug-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples DSLVDS1002dbvr preview sot-23 dbv 5 1000 tbd call ti call ti -40 to 85 DSLVDS1002dbvt preview sot-23 dbv 5 1000 tbd call ti call ti -40 to 85 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.

www.ti.com package outline c typ 0.22 0.08 0.25 3.0 2.6 2x 0.95 1.9 1.45 max typ 0.15 0.00 5x 0.5 0.3 typ 0.6 0.3 typ 8 0 1.9 a 3.05 2.75 b 1.75 1.45 (1.1) sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. refernce jedec mo-178. 0.2 c a b 1 3 4 5 2 index area pin 1 gage plane seating plane 0.1 c scale 4.000
www.ti.com example board layout 0.07 max arround 0.07 min arround 5x (1.1) 5x (0.6) (2.6) (1.9) 2x (0.95) (r0.05) typ 4214839/c 04/2017 sot-23 - 1.45 mm max height dbv0005a small outline transistor notes: (continued) 4. publication ipc-7351 may have alternate designs. 5. solder mask tolerances between and around signal pads can vary based on board fabrication site. symm land pattern example exposed metal shown scale:15x pkg 1 3 4 5 2 solder mask opening metal under solder mask solder mask defined exposed metal metal solder mask opening non solder mask defined (preferred) solder mask details exposed metal
www.ti.com example stencil design (2.6) (1.9) 2x(0.95) 5x (1.1) 5x (0.6) (r0.05) typ sot-23 - 1.45 mm max height dbv0005a small outline transistor 4214839/c 04/2017 notes: (continued) 6. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 7. board assembly site may have different recommendations for stencil design. solder paste example based on 0.125 mm thick stencil scale:15x symm pkg 1 3 4 5 2
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